1. Field of Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a dual damascene process.
2. Description of Related Art
In a conventional method of fabricating multilevel interconnects, a metal layer is deposited on an insulating layer, such as an oxide layer. The metal layer is then defined to form a conductive line. A dielectric layer having an opening is formed over the conductive line, and the conductive line is exposed by the opening. The opening is filled with a metal layer so as to be electrically connected with the conductive line. With an increase of required conductive layers in integrated circuits, more than two conductive layers are necessary according to the design rule. An inter-metal dielectric (IMD) layer is usually formed between two conductive layers in order to insulate the conductive layers. A conductive line is formed between the two conductive layers as an electrical connection. The conductive line is called a via in the semiconductor industry.
In a conventional method, the via and the interconnects are formed in different steps. A dielectric layer is formed on a metal layer. A photoresist layer is formed on the dielectric layer. Using the photoresist layer as a mask, the dielectric layer is etched. A via hole is formed in the dielectric layer, and the metal layer is exposed by the via hole. A conductive material is formed by deposition. At this stage, a complete via is formed. Then, a metal layer is formed over the dielectric layer. The metal layer is defined. Finally, an inter-metal dielectric layer is deposited. By this method, interconnects are formed. However, since the conventional method is to first form the via, and then to form the metal layer, misalignment easily occurs while forming the subsequent metal layer. Misalignment causes an error in the integrated circuits (IC) and a decrease of device yield.